MWPR1024IZVHT datasheet(44/86 Pages) NXP

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Table 19. Device clock specifications (continued)

Symbol

Description

Min.

Max.

Unit

VLPR and VLPS modes1

fSYS

System and core clock

—

MHz

fBUS

Bus clock

—

MHz

fFLASH

Flash clock

—

MHz

fLPTMR

LPTMR clock2

—

MHz

fERCLK

External reference clock

—

MHz

fLPTMR_ERCLK LPTMR external reference clock

—

MHz

fTPM

TPM asynchronous clock

—

MHz

fLPUART0

LPUART0 asynchronous clock

—

MHz

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing

specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN

or from VLPR.

2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

7.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO,

LPUART, CMT and I2C signals.

Table 20. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter disabled)

— Synchronous path

1.5

—

Bus clock cycles

1, 2

NMI_b pin interrupt pulse width (analog filter enabled) —

Asynchronous path

200

—

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter disabled) — Asynchronous path

—

External RESET_b input pulse width (digital glitch filter

disabled)

100

—

Port rise and fall time(high drive strength)

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

—

4, 5

Port rise and fall time(low drive strength)

• Slew enabled

—

6, 7

MCU Electrical Characteristics

MWPR1124ZVHT/MWPR1024IZVHT Data Sheet, Rev. 0, 04/2018

NXP Semiconductors

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