PCF85363ATLSLASHA datasheet(58/86 Pages) NXP

58 / 86 page

NXP Semiconductors

PCF85363A

Tiny Real-Time Clock/calendar with 64 byte RAM, alarm function, battery switch-over time stamp input,

and I2C-bus

SCL

SDA

ACK

aaa-010489

SCL

SDA

bit7

bit0 ACK

ACK

START

condition

STOP

condition

ACK of 1st byte

from slave

ACK of 2nd byte

from slave

I2C read example

I2C write example

bit7

bit0

1st byte, slave address with R/W = 0

write 2nd byte

START

condition

STOP

condition

1st byte, slave address with R/W = 1

ACK of 1st byte

from slave

ACK of 2nd byte

from slave

bit7

bit0

bit7

bit0

read 2nd byte

Figure 33. I2C read and write signaling

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse, as changes in the data line at

this time are interpreted as STOP or START conditions.

8.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the

START condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 33).

8.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitter, it

must generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

A detailed description of the I2C-bus specification is given in [4].

PCF85363A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 18 June 2021

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