Turn on Sequence (continue)

Input voltage levels for the I/O control lines:

15. The evaluation board also included an integrator (op-amp circuitry, if the option is loaded) which

generates a Vtune error voltage output signal at the Vtune port (2.9 mm (f) connector). This

signal can be viewed using a spectrum analyzer or oscilloscope. See the Application Notes

section for additional information.

This error voltage represented the phase frequency difference between the REF and VCO input

signals (~ 10 MHz signal, the average of this signal is the VCO’s dc error correction voltage).

16. Refer to PFD1K datasheet for performance specifications.

Pin Descriptions:

Pin #

Port Name

Description

Notes

34

REFP

Reference RF input, positive terminal

CML signal levels

35

REFN

Reference RF input, negative terminal

CML signal levels

17

VCOP

VCO RF input, positive terminal

CML signal levels

16

VCON

VCO RF input, negative terminal

CML signal levels

26

UPP

Up Charge Pump output, positive terminal

CML output level set by charge pump gain

27

UPN

Up Charge Pump output, negative terminal

CML output level set by charge pump gain

25

DNP

Down Charge Pump output, positive terminal

CML output level set by charge pump gain

24

DNN

Down Charge Pump output, negative terminal

CML output level set by charge pump gain

31

DRO

Divided Reference Output ( single ended )

CML output level, requires DC pullup

20

DVO

Divided VCO Output ( single ended )

CML output level, requires DC pullup

Pin #

Port

Name

Description

Notes

8

POL

Polarity of Phase Detector

3.3 V CMOS levels, defaults to logic 0 if open

2, 1, 40, 39, 38,

37, 36

R[6:0]

Reference Prescaler Divide Ratio

3.3 V CMOS levels, defaults to logic 0 if open

9, 10, 11, 12,

13, 14, 15

V[6:0]

VCO Prescaler Divide Ratio

3.3 V CMOS levels, defaults to logic 0 if open

7, 6, 5, 4

A[3:0]

Charge Pump Gain Control

3.3 V CMOS levels, defaults to logic 0 if open

3

VADJ

Charge Pump Gain Analog Control

From VEE to VCC, VCC for max output

30

VADR

Divided Reference Output Level Control From VEE to VCC, VCC for max output

21

VADV

Divided VCO Output Level Control

From VEE to VCC, VCC for max output

32, 19, 23, 28

VCC1-4 Positive power supply

+3.3 V @ 500 mA

33, 18, 22, 29

VEE1-4 Negative power supply

Ground

Paddle

Paddle

Package Paddle

Tie to heatsink

Logic Level

Minimum

Typical

Maximum

1 (High)

VCC-1.3V

VCC

VCC

0 (Low)

VEE

VEE

VEE + 0.8V

16 of 19

SMD-00191 Rev D

Subject to Change Without Notice

PFD1K