© VITESSE SEMICONDUCTOR CORPORATION

Page 13

11/9/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8131

2.488 Gbit/sec

32:1 SONET/SDH Mux with Clock Generator

G52249-0, Rev. 3.0

NC = No Connection. These pins must be left floating - do not connect to a supply potential. Connecting any of these pins to a

power supply rail may cause improper operation or failure of the device; or in extreme cases, may cause permanent dam-

age to the device.

PARBIT

111

I

TTL

parity bit

PARMODE

112

I

TTL

parity mode select (even vs. odd)

VCC

113

PWR

+3.3V

TEST

114

I

GND

NC

115

-

-

Leave Unconnected

REFCLK+

116

I

LVPECL

CMU reference clock, true

REFCLK-

117

I

LVPECL

CMU reference clock, compliment

VCC

118

PWR

+3.3V

VEE

119

PWR

GND

TEST

120

O

-

Leave Unconnected

TEST

121

O

-

Leave Unconnected

VEE_ANA

122

PWR

GND

Analog Power for CMU

VCC_ANA

123

PWR

+3.3V

Analog Power for CMU

NC

124

-

-

Leave Unconnected

NC

125

-

-

Leave Unconnected

VEE

126

PWR

GND

VEE

127

PWR

GND

VCC

128

PWR

+3.3V

Table 4: Package Pin Identification

Signal

Pin

I/O

Level

Pin Description