Data Sheet

ADAQ23876

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 11 of 37

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

B10

CNV−

DI

Conversion Start LVDS Input. A rising edge on CNV+ puts the internal sample-and-hold in hold mode

and starts a conversion cycle. CNV+ can be also driven with a 2.5 V CMOS signal if CNV− is

connected to GND.

C1, D1

OUT+

AO

Positive Output of the FDA.

C2, C4, E4, H1

VS+

P

FDA and Reference Buffer Positive Supply. The LDO output generating the VS+ supply of µModule

must be bypassed with at least 2.2 μF (0402, X5R) ceramic capacitor to GND.

C3, D3

OUT−

AO

Negative Output of the FDA

C5, J1

VS−

P

FDA Negative Supply. Bypass this pin to GND with an at least 2.2 μF (0402, X5R) ceramic capacitor.

D6

VCMO

AO

FDA Output Common-Mode Voltage. This pin is nominally REFBUF/2.

D10

CLK+

DI

LVDS Clock Input. This pin is an externally applied clock that serially shifts out the conversion result.

E10

CLK−

DI

LVDS Clock Input. This is an externally applied clock that serially shifts out the conversion result.

F1, F2

NC

No Connect.

G10

DCO+

DO

LVDS Data Clock Output. This is an echoed version of CLK+/CLK− that can be used to latch the data

outputs.

H10

DCO−

DO

LVDS Data Clock Output. This is an echoed version of CLK+/CLK− that can be used to latch the data

outputs.

J3, J4

REFBUF

AO

Reference Buffer Output Voltage. As a required component of SAR architecture, a 10 μF ceramic

bypass capacitor is already laid out within the ADAQ23876 between REFBUF and GND. Therefore,

adding a second, smaller capacitor in parallel with the 10 μF capacitor may degrade performance

and is not recommended. The common-mode voltage of VCMO and LVDS pins are derived from the

REFBUF. Therefore, a voltage at REFBUF pin must be stable after the ADAQ23876 is powered on or

exits power-down mode before starting a conversion cycle.

J10

DA+

DO

Serial LVDS Data Output. In one-lane output mode, DB−/DB+ are not used and their LVDS driver is

disabled to reduce power consumption.

K3

REFIN

P

Internal Reference Output/Reference Buffer Input. The output voltage of the internal reference,

nominally 2.048 V, is output on this pin. An external reference can be applied to REFIN if a more

accurate reference is required. If the internal reference buffer is not used, connect REFIN to GND to

power down the buffer and connect an external buffered reference to REFBUF.

K5

PDB_ADC

DI

Digital Input that Enables the Power-Down Mode. When PDB_ADC is low, an internal ADC core enters

power-down mode, and all circuitry (including the LVDS interface) is shutdown. When PDB_ADC is

high, the device operates normally. Logic levels are determined by VIO.

K6

VDD

P

5 V Analog Power Supply. The range of VDD is 4.75 V to 5.25 V. Bypass the VDD pin to GND with an

at least 2.2 μF (0402, X5R) ceramic capacitor.

K7

TESTPAT

DI

Digital Input that Forces the LVDS Data Outputs to be a Test Pattern. When TESTPAT is high,

the digital outputs are test pattern. When TESTPAT is low, the digital outputs are the ADAQ23876

conversion result. Logic levels are determined by VIO.

K8

DB−

DO

Serial LVDS Data Output. In one-lane output mode, DA−/DA+ are not used and their LVDS driver is

disabled to reduce power consumption.

K9

DB+

DO

Serial LVDS Data Outputs. In one-lane output mode, DA−/DA+ are not used and their LVDS driver is

disabled to reduce power consumption.

K10

DA−

DO

Serial LVDS Data Outputs. In one-lane output mode, DB−/DB+ are not used and their LVDS driver is

disabled to reduce power consumption.