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STM32F730V8 Datasheet(PDF) 175 Page - STMicroelectronics |
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STM32F730V8 Datasheet(HTML) 175 Page - STMicroelectronics |
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175 / 202 page  DS12536 Rev 2 175/202 STM32F730x8 Electrical characteristics 185 NAND controller waveforms and timings Figure 61 through Figure 64 represent synchronous waveforms, and Table 105 and Table 106 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01; • COM.FMC_WaitSetupTime = 0x03; • COM.FMC_HoldSetupTime = 0x02; • COM.FMC_HiZSetupTime = 0x01; • ATT.FMC_SetupTime = 0x01; • ATT.FMC_WaitSetupTime = 0x03; • ATT.FMC_HoldSetupTime = 0x02; • ATT.FMC_HiZSetupTime = 0x01; • Bank = FMC_Bank_NAND; • MemoryDataWidth = FMC_MemoryDataWidth_16b; • ECC = FMC_ECC_Enable; • ECCPageSize = FMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 104. Synchronous non-multiplexed PSRAM write timings(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit t(CLK) FMC_CLK period 2Thclk - 0.5 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2 t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Thclk +1 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 - |
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