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STM32G0 Datasheet(PDF) 34 Page - STMicroelectronics

Part # STM32G0
Description  Arm® Cortex®-M0 32-bit MCU, up to 128 KB Flash, 36 KB RAM, 4x USART, timers, ADC, DAC, comm. I/Fs, 1.7-3.6V
PDF  135 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G0 Datasheet(HTML) 34 Page - STMicroelectronics

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Functional overview
STM32G071x8/xB
34/135
DS12232 Rev 4
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.23
Serial peripheral interface (SPI)
The device contains two SPIs running at up to 32 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
The I2S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.
3.24
USB Type-C™ Power Delivery controller
The device embeds two controllers (UCPD1 and UCPD2) compliant with USB Type-C Rev.
1.2 and USB Power Delivery Rev. 3.0 specifications.
The controllers use specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•
USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
•
“Dead battery” support
•
USB Power Delivery message transmission and reception
•
FRS (fast role swap) support
Table 10. SPI/I2S implementation
SPI features(1)
1. X = supported.
SPI1
SPI2
Hardware CRC calculation
X
X
Rx/Tx FIFO
X
X
NSS pulse mode
X
X
I2S mode
X
-
TI mode
X
X



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