STA369BWSTR datasheet(76/92 Pages) STMICROELECTRONICS

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STA369BWS

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DocID016861 Rev 7

Figure 23. Short-circuit detection timing diagram (no short detected)

In Figure 23 the short protection timing diagram is shown. The time information is expressed

in clock cycles, where the clock frequency is defined as in section . The grey colour is used

for SHOK bits to indicate that the bits keep the status of the previous EAPD 0 -> 1 toggling.

NB that after reset this state is meaningless until an EAPD transition has occurred. Ground

related SHOK bits are updated as soon as the GND test is completed, while VCC bits are

updated after the VCC test is completed. Both GND and VCC tests are always run (if SHEN

bit active and EAPD toggled to 1), and only if both test are successful (no short) will the

bridge outputs leave the 3-state (indicated in dotted lines in the figure). If one of the two

tests (or both) fail, the power bridge outputs are kept in 3-state until the procedure is

restarted with a new EAPD toggling.

In this figure EAPD is bit 7 of register 0x05.

7.18

Quantization error noise correction (addr 0x48)

A special feature inside the digital processing block is available. In case of poles positioned

at very low frequencies, biquads filters, can generate some audible quantization noise or

unwanted DC level. In order to avoid such kind of effect a quantization noise shaping

capability can be used. The filter structure including this special feature, relative to each

biquad is shown in Figure 24.

To maintain a back compatibility with all the previous Sound Terminal® products the feature

is not activated by default. It can be enabled independently for each biquad using I2C

NSHXEN

NSHB7EN

NSHB6EN

NSHB5EN

NSHB4EN

NSHB3EN

NSHB2EN

NSHB1EN

00000000

STA369BWSTR Datasheet(PDF) 76 Page - STMicroelectronics