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Two-PLL Clock Generator with
Direct Rambus™ (Lite) Support
CY22313
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07434 Rev. *E
Revised June 29, 2004
Features
• Two integrated phase-locked loops (PLLs)
• Ultra-accurate PLLs
• Direct Rambus™ clock support
• Two input selects
• 3.45V core; 3.45V, 2.5V, 1.8V, and 1.675V outputs
• 24-pin TSSOP package
Benefits
• High-performance PLL tailored for multimedia applica-
tions
• Frequency tolerance within 1 PPM on all frequencies
• One pair of differential output drivers, identical speci-
fication to CY2212
• Selectable 54.0-/53.946-MHz output and
294.912-/393.216-MHz Rambus® output
• Supports output voltage requirements
• Industry-standard packaging saves on board space
Pin Configuration
Frequency Select Tables
XIN
XOUT
S
FS
OSC.
PLL1
LCLK
Divider
CLK
54MOUT
Block Diagram
PLL2
CLKB
Divide by 2
XTAL.
CONFIGURATION
LOGIC
VDDRP
1
24
S
VSSRP
2
23
VDDR
Xout
3
22
VSSR
Xin
4
21
CLK
NC
5
20
CLKB
VSSVPA
6
19
VSSR
VDDVPA
7
18
VDDR
VSS54
8
17
NC
54MOUT
9
16
VDDL
FS
10
15
VSSL
VDD54
11
14
LCLK
VDDVP
12
13
VSSVP
FS
54MOUT
Unit
PPM
054
MHz
0
1
53.94605395
MHz
–1
S
CLK, CLKB
Unit
PPM
0
294.912
MHz
0
1
393.216
MHz
0
LCLK
Unit
PPM
9.216
MHz
0