DS90C387RVJD datasheet(11/28 Pages) NSC

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DS90C387R Pin Description—LDI

Transmitter

Pin Name

I/O

No.

Description

D0-D23

LVTTL level single-ended inputs or low swing pseduo differential inputs.

Reference to V

REF pin.

D0-D11 are for 12-bit input mode (24 RGB data); D0-D11 (first 12-bit port)

and D12-D23 (second 12-bit port) are for two 12-bit input mode (48 RGB

data).

LVTTL level or low swing level inputs for data enable. This signal is HIGH

when input pixel data is valid to DS90C387R provided that R_FDE = HIGH.

HSYNC

Horizontal Sync input control signal. LVTTL level or low swing level.

VSYNC

Vertical Horizontal Sync input control signal. LVTTL level or low swing level.

AnP

Positive LVDS differential data output.

AnM

Negative LVDS differential data output.

CLKINP

In LVTTL level operation, this is a single-ended clock. In low swing

operation, this is the positive differential clock input .

CLKINM

In LVTTL level operation, no connect or connect to V

REF pin. Do not connect

to GND under any condition. In low swing operation, this is negative

differential clock input .

R_FB

LVTTL level input for selecting the Primary clock edge E1. Falling clock

edge selected when input is HIGH; Rising clock edge selected when input is

LOW.(Note 14)

R_FDE

LVTTL level input. Programmable control (DE) strobe select. Tie HIGH for

data active when DE is HIGH. (Note 14)

CLK1P

Positive LVDS differential clock output.

CLK1M

Negative LVDS differential clock output.

LVCMOS level input. Input = LOW will place the entire device in power down

mode. Outputs of the device will be in TRI-STATE mode to ensure low

current at power down. (Note 14)

Input = HIGH for normal operation.

PLLSEL

LVTTL level in. Tie to Vcc for normal operation. (Note 14)

BAL

LVTTL level input. Mode select for dc balanced or non-dc balanced

interface. DC balance is active when input is high. (Note 14)

PRE

Pre-emphasis level select. Pre-emphasis is active when input is tied to V

through external pull-up resistor. Resistor value determines pre-emphasis

level (see table in application section). For normal LVDS drive level

(minimum pre-emphasis) leave this pin open (do not tie to ground).(Note 14)

DUAL

LVTTL level input. Input = LOW for one 12-bit input mode, 24 RGB data in,

24 RGB data out.(Note 14)

LVTTL level input. Input = V

CC for two 12-bit input mode, 48 RGB data in,

48 RGB data out.(Note 14)

Connect to power supply with voltage stated under ” Recommended

Operating Conitions ” on page 3. Power supply pin for LVTTL inputs and

digital circuitry, pin53.

GND

Ground pins for LVTTL inputs and digital circuitry, pins 9, 11, 52, 77.

I2V

Connect to power supply with voltage stated under ” Recommended

Operating Conitions ” on page 3, pin 68.

CC3V

Connect to power supply with voltage stated under ” Recommended

Operating Conitions ” on page 3, pins 70, 79, 95.

GND

Ground pin(s) for powering the data inputs, pins 71, 80, 96.

SGND

Connect to ground, pin 69.

DS90C387RVJD Datasheet(PDF) 11 Page - National Semiconductor (TI)

DS90C387RVJD Datasheet(HTML) 11 Page - National Semiconductor (TI)

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