M68AW256DL datasheet(12/20 Pages) STMICROELECTRONICS

12 / 20 page

M68AW256DL

12/20

Write Mode

The M68AW256DL, when Chip Select (E2) is

High, is in the Write Mode whenever the W and E1

are Low. Either the Chip Enable Input (E1) or the

Write Enable input (W) must be de-asserted dur-

ing Address transitions for subsequent write cy-

cles. When E1 or W is Low, and UB or LB is Low,

write cycle begins on the W or E1 falling edge.

When E1 and W are Low, and UB = LB = High,

write cycle begins on the first falling edge of UB or

LB. Therefore, address setup time is referenced to

Write Enable, Chip Enables and UB/LB as tAVWL,

tAVEL and tAVBL respectively, and is determined by

the latter occurring falling edge.

The Write cycle can be terminated by the earlier

rising edge of E1, W, UB and LB.

If the Output is enabled (E1 = Low, E2 = High, G =

Low, LB or UB = Low), then W will return the

outputs to high impedance within tWLQZ of its

falling edge. Care must be taken to avoid bus

contention in this type of operation. Data input

must be valid for tDVWH before the rising edge of

Write Enable, or for tDVEH before the rising edge of

E1 or for tDVBH before the rising edge of UB/LB,

whichever occurs first, and remain valid for tWHDX,

tEHDX and tBHDX respectively.

Figure 11. Write Enable Controlled, Write AC Waveforms

AI05498

tAVAV

tWHAX

tDVWH

DATA INPUT

A0-A17

DQ0-DQ15

VALID

tAVWH

tAVEL

tWLWH

tAVWL

tWLQZ

tWHDX

tWHQX

tBLBH

UB, LB

tELWH

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