ADP2126 datasheet(13/20 Pages) AD

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Data Sheet

ADP2126/ADP2127

Rev. B | Page 13 of 20

reshold, EXTCLK must be powered with the logic high signal

whe

d Figure 3 for the timing specifications and

PROTECTION FEATURES

Overcurrent Protection

To ensure that excessively high currents do not damage the

MOSFET switches, the ADP2126/ADP2127 incorporate cycle-by-

cycle overcurrent protection. This function is accomplished by

monitoring the instantaneous peak current on the power PMOS

switch. If this current exceeds the PMOS switch current limit

(1 A typical), then the PMOS is immediately turned off. This

minimizes the potential for damage to power components during

certain faults and transient events.

Output Short-Circuit Protection (SCP)

If the output voltage is shorted to GND, a standard dc-to-dc

controller delivers maximum power into that short. This may

result in a potentially catastrophic failure. To prevent this, the

ADP2126/ADP2127 sense when the output voltage is below the

SCP threshold (typically 0.52 V). At this point, the controller

turns off for approximately 450 μs and then automatically initiates a

soft start sequence. This cycle repeats until the short is removed

or the part is disabled. Figure 16 shows the operating behavior of

the ADP2126/ADP2127 during a short-circuit fault. The SCP

dramatically reduces the power delivered into the short circuit,

yet still allows the converter to recover when the fault is removed.

Thermal Shutdown (TSD) Protection

The ADP2126/ADP2127 also include TSD protection when the

part is in PWM mode only. If the die temperature exceeds 146°C

(typical), the TSD protection activates and turns off both MOSFET

power devices. They remain off until the die temperature falls to

133°C (typical), at which point the regulator restarts.

Undervoltage Lockout (UVLO)

If the input voltage drops below the UVLO falling threshold, the

ADP2126/ADP2127 automatically turn off the power switches and

enter a low power consumption mode. This prevents potentially

erratic operation at low input voltages. The parts remain in this

state until the input voltage rises above the UVLO rising threshold.

The UVLO levels have approximately 100 mV of hysteresis to

ensure glitch-free startup.

For the logic high enable option, during startup and UVLO

recovery after the input voltage drops below the UVLO falling

after VIN. If VIN dips below the UVLO falling threshold and

EXTCLK is powered before VIN with a logic high signal, the

UVLO does not become active. If VIN and EXTCLK are

powered from the same source, an RC circuit (see Figure 1)

is recommended to ensure that the ADP2126/ADP2127 are

powered correctly. Rτ and Cτ should be selected so that the

RC time constant (τ) is greater than the 200 μs minimum

specification for VIN high to EXTCLK on (t1). τ is calculat

using the following equation:

τ = Rτ × Cτ

re τ ≥ t1.

See Table 1 an

diagrams.

VIN

EXTCLK

GND

OFF

VIN

CIN

()

Figure 29. Recommended Logic Enable Startup Ci

TIMING CO

6/ADP2127 enter shutdown mode after the

ereby triggering UVLO, the ADP2126/

rcu

NSTRAINTS

Shutdown Time

When the ADP212

EXTCLK signal is removed, the ADP2126/ADP2127 must remain

in shutdown mode for a minimum of 1400 μs, if no load is applied,

before the EXTCLK signal can be reapplied. This allows all internal

nodes to discharge to an off state.

Power-Off Time

When VIN drops, th

ADP2127 have a minimum power-off time (t7) of 500 μs tha

must elapse before VIN can be reapplied. This allows all intern

nodes to discharge enough power so that all internal devices are

in an off state.

VIN × 10%

Figure 30. Power-Off Time

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