M64892AFP/GP

SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

5

METHOD OF SETTING DATA

The frequency demultiplying ratio uses 15bits. Setting up the band

switching output uses 4bits.

The test mode data uses 8bits. The total bits used is 27bits. Data is

read in when the enable signal is "H" and the clock signal falls.

The band switching data is read in at the 4th pulse of the clock

signal. The program counter data is read into the latch by the fall of

the enable signal after the 18th pulse of the clock signal or the fall of

the 19th pulse of the clock signal. When the enable signal goes to

"L" before the 18th pulse of the enable signal, only the band SW

data is updated and other data is ignored.

The shift register is equipped with the 18/19 bit automatic decision

function. When the 18th bit data is used, the M9 bit of the program

counter is reset and the 1/512 division of the reference frequency is

set. In case of the 19th bit, 1/1024 division of the reference

frequency is set.

M8

BS4

BS3

BS2

BS1

ENA

DATA

CLK

BAND SW

DATA

READ INTO LATCH

M COUNTER DIVISION

RATIO SETTING

S COUNTER DIVISION

RATIO SETTING

READ INTO LATCH

M7

M6

M5

M4

M3

M2

M1

M0

S4

S3

S2

S1

S0

(2) Transfer of the 19th bit data

The data is latched at the 19th pulse of the clock signal. At this time,

1/1024 frequency division ratio is used. Clock signals after the

above are invalid.

Notice) To change reference frequency, set up as ENA in "L" after

19th pulse of clock signal by all means

M8

BS4

BS3

BS2

BS1

ENA

DATA

CLK

BAND SW

DATA

READ INTO LATCH

M COUNTER DIVISION

RATIO SETTING

S COUNTER DIVISION

RATIO SETTING

READ INTO LATCH

M7

M6

M5

M4

M3

M2

M1

M0

S4

S3

S2

S1

S0

M9

(1) Transfer of the 18th bit data

Data is latched by the fall of the enable signal after the 18th clock

signal. At this time, the division of the 1/512 of the reference

frequency is used.