MIMXRT8024DFP4A datasheet(52/72 Pages) NXP

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i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 3.1, 03/2022

NXP Semiconductors

Electrical characteristics

Figure 30. Minimum Sample Time Vs Ras (Cas = 10 pF)

4.8

Communication interfaces

The following sections provide the information about communication interfaces.

4.8.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Table 45. LPSPI Master mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

fSCK

Frequency of operation

—

fperiph / 2

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be

guaranteed this limit is not exceeded.

tSCK

SCK period

2 x tperiph

—

2 tperiph = 1 / fperiph

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

—

tSU

Data setup time (inputs)

—

tHI

Data hold time (inputs)

—

Data valid (after SCK edge)

—

tHO

Data hold time (outputs)

—

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