PIC18F2450-ESLASHPTSQTP datasheet(77/320 Pages) MICROCHIP

77 / 320 page

PIC18F2450/4450

Advance Information

DS39760A-page 75

EECON1: MEMORY CONTROL REGISTER 1

U-0

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

U-0

—CFGS

—

FREE

WRERR(1)

WREN

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6

CFGS: Flash Program or Configuration Select bit

= Access Configuration registers

= Access Flash program

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write-only

bit 3

WRERR: Flash Program Error Flag bit(1)

= A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation or an improper write attempt)

= The write operation completed

bit 2

WREN: Flash Program Write Enable bit

= Allows write cycles to Flash program

= Inhibits write cycles to Flash program

bit 1

WR: Write Control bit

= Initiates a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

= Write cycle complete

bit 0

Unimplemented: Read as ‘0’

Note 1:

When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition.

PIC18F2450-E/PTSQTP Datasheet(PDF) 77 Page - Microchip Technology

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