4

ICS932S200

0427C—07/03/02

Power Management Requirements:

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes

low/high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.

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CPU_STOP# Timing Diagram

CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for

low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge

of free running PCI clock (and hence CPU clock) and must be internally synchronized to the external output. All other

clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state

and started in such a manner as to guarantee that the high pulse width is a full pulse.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. The internal label means inside the chip and is a reference only.

This in fact may not be the way that the control is designed.

3. 3V66 clocks also stop/start before

4. PD# and PCI_STOP# are shown in a high state.

5. Diagrams shown with respect to 133MHz. Similar operation when

CPU is 100MHz

CPUCLK

(internal)

(internal)

(externall)

(externall)

PCICLK

PCI_STOP#

CPU_STOP#

PD#

CPUCLK

3V66