MCP6V5XTESLASHMS datasheet(24/50 Pages) MICROCHIP

24 / 50 page

MCP6V51/2/4

DS20006136B-page 24



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To derive the power dissipation of the device, add the

terms for the devices’ quiescent power and the load

power, as shown in Equation 4-2:

EQUATION 4-2:

This assumes that the device is sourcing the load

current (i.e., current flowing from the VDD supply into

the load). Use the term (IOUT ×(VOUT – VSS)) when the

device is sinking current. Note that this simple example

assumes a constant (DC) signal current flow.

The thermal shutdown circuitry activates as soon as

the junction temperature reaches approximately

+175°C, causing the amplifier’s output stage to be tri-

stated (high-impedance), effectively disabling any

output current flow. The amplifier will remain in this

disabled state until the junction temperature has cooled

down to approximately +160°C. At this point, the

thermal shutdown circuitry will enable the output stage

of the MCP6V5X amplifier and the device will resume

normal operation.

If a Fault condition persists, for example, the amplifier’s

output (VOUT) is shorted causing excessive output

current, the thermal shutdown circuity may be triggered

again and the previously described cycle repeats. This

may continue until the Fault condition is removed.

It should be noted that the thermal shutdown feature of

the MCP6V5X does not ensure that the device will

remain undamaged when operated under stress

conditions, during which the device is placed into the

Shutdown mode.

4.3

Application Tips

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

The

DC Electrical Specifications table gives both the

linear and quadratic temperature coefficients (TC1 and

TC2) of the input offset voltage. The input offset

voltage, at any temperature in the specified range, can

be calculated as follows:

EQUATION 4-3:

4.3.2

DC GAIN PLOTS

Figure 2-8, Figure 2-9 and Figure 2-10 are histograms

of the reciprocals (in units of µV/V) of CMRR, PSRR

and AOL, respectively. They represent the change in

Input Offset Voltage (VOS) with a change in Common-

Mode Input Voltage (VCM), Power Supply Voltage

(VDD) and Output Voltage (VOUT).

The 1/AOL histogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s

input noise. The negative values shown represent

noise and tester limitations, not unstable behavior.

Production tests make multiple VOS measurements,

which validates an op amp’s stability; an unstable part

would show greater VOS variability or the output would

stick at one of the supply rails.

4.3.3

OFFSET AT POWER-UP

When these parts power up, the Input Offset (VOS)

starts at its uncorrected value (usually less than

±5 mV). Circuits with high DC gain may cause the

output to reach one of the two rails. In this case, the

time to a valid output is delayed by an Output Overdrive

Time (tODR), in addition to the Start-up Time (tSTR).

To avoid this extended start-up time, reducing the gain

is one method. Adding a capacitor across the

Feedback Resistor (RF) is another method.

4.3.4

SOURCE RESISTANCES

The input bias currents have two significant

components: switching glitches that dominate at room

temperature and below, and input ESD diode leakage

currents that dominate at +85°C and above.

Make the resistances seen by the inputs small and

equal. This minimizes the output offset voltage caused

by the input bias currents.

The inputs should see a resistance in the order of 10Ω

to 1 kΩ at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which

are very fast, on overall performance. In some cases, it

may be necessary to add resistors in series with the

inputs to achieve this improvement in performance.

Small input resistances may be needed for high gains.

Without them, parasitic capacitances might cause

positive feedback and instability.

4.3.5

SOURCE CAPACITANCE

The capacitances seen by the two inputs should be

small. Large input capacitances and source

resistances, together with high gain, can lead to

instability.

VDD VSS

–





IQ IOUT VDD VOUT

–







VOS TA

 

VOS TC1T TC2T

Where:



T = TA – 25°C

VOS(TA) = Input offset voltage at TA

VOS = Input offset voltage at +25°C

TC1 = Linear temperature coefficient

TC2 = Quadratic temperature coefficient

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