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BQ24070 Datasheet(PDF) 21 Page - Texas Instruments |
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BQ24070 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 26 page ![]() www.ti.com APPLICATION INFORMATION Selecting the Input and Output Capacitors Thermal Considerations q JA + T J * TA P (9) P + VIN * VOUT I OUT ) IBAT ) VOUT * VBAT I BAT (10) bq24070 SLUS694A – MARCH 2006 – REVISED MARCH 2006 In most applications, all that is needed is a high-frequency decoupling capacitor on the input. A 0.1-µF ceramic capacitor, placed in close proximity to IN to VSS pins, works well. In some applications depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-µF ceramic capacitor to the input. The bq24070 only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed between the OUT and VSS pin is typically sufficient. It is recommended to install a minimum of 33-µF capacitor between the BAT pin and VSS (in parallel with the battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached). The bq24070 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal performance is thermal impedance ( θ JA) measured (or modeled) from the chip junction to the air surrounding the package surface (ambient). The mathematical expression for θ JA is: where TJ = chip junction temperature TA = ambient temperature P = device power dissipation Factors that can greatly influence the measurement and calculation of θ JA include: • whether or not the device is board mounted • trace size, composition, thickness, and geometry • orientation of the device (horizontal or vertical) • volume of the ambient air surrounding the device under test and airflow • whether other surfaces are in close proximity to the device being tested The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power FET. It can be calculated from Equation 10: Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 1. Typically the Li-ion battery's voltage quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum battery voltage because the system board and charging device does not have time to reach a maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and chargers power pad temperature. 21 Submit Documentation Feedback |
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