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RA2E2 Datasheet(PDF) 24 Page - Renesas Technology Corp

Part # RA2E2
Description  Ultra low power 48 MHz Arm® Cortex®-M23 core, up to 64-KB code flash memory, 8-KB SRAM, 12-bit A/D Converter, Security and Safety features.
PDF  98 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RA2E2 Datasheet(HTML) 24 Page - Renesas Technology Corp

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Table 2.19
Clock timing (2 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
HOCO clock oscillation frequency*3
fHOCO24
23.76
24
24.24
MHz
Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
fHOCO32
31.68
32
32.32
Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
fHOCO48
47.52
48
48.48
Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
fHOCO64
63.36
64
64.64
Ta = -40 to 125°C
1.6 ≤ VCC ≤ 5.5
HOCO clock oscillation stabilization time*1 *2
tHOCO24
tHOCO32
tHOCO48
tHOCO64
—
6.7
7.7
µs
Figure 2.4
Note 1. This is a characteristic when the HOCOCR.HCSTP bit is set to 0 (oscillation) in the MOCO stop state. When the HOCOCR.HCSTP
bit is set to 0 (oscillation) during MOCO oscillation, this specification is shortened by 1 µs.
Note 2. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
Note 3. Accuracy at production test.
LOCO clock oscillator output
LOCOCR.LCSTP
tLOCO
Figure 2.3
LOCO clock oscillation start timing
HOCO clock
HOCOCR.HCSTP
tHOCOx*1
Note:
x = 24, 32, 48, 64
Figure 2.4
HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
2.3.3
Reset Timing
Table 2.20
Reset timing (1 of 2)
Parameter
Symbol
Min
Typ
Max
Unit
Test
conditions
RES pulse width
At power-on
tRESWP
10
—
—
ms
Figure 2.5
Not at power-on
tRESW
30
—
—
µs
Figure 2.6
Wait time after RES cancellation (at
power-on)
LVD0 enabled*1
tRESWT
—
0.9
—
ms
Figure 2.5
LVD0 disabled*2
—
0.2
—
RA2E2 Datasheet
2. Electrical Characteristics
R01DS0387EJ0110 Rev.1.10
Mar 31, 2022
Page 24 of 98



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