ZMOD4410 Datasheet

© 2021 Renesas Electronics Corporation

18

December 17, 2021

Table 11. Bus Timing Characteristic

Parameter

Symbol

Standard Mode

Fast Mode

Unit

Maximum SCL clock frequency

100

400

kHz

Minimum START condition hold time relative to SCL edge

4

µs

Minimum SCL clock low width

4.7

µs

Minimum SCL clock high width

4

µs

Minimum START condition setup time relative to SCL edge

4.7

µs

Minimum data hold time on SDA relative to SCL edge

0

µs

Minimum data setup time on SDA relative to SCL edge

0.1

0.1

µs

Minimum STOP condition setup time on SCL

4

µs

Minimum bus free time between stop condition and start condition

4.7

µs

12. Related Websites and Software

Visit the ZMOD4410 and ZMOD4410 Evaluation Kit (ZMOD4410-EVK) webpages on the Renesas website to download software and the latest

version of related documents, such as application notes, white papers, product briefs, and third-party reports.

Note that some documents require logging in with a free customer account, which can be set up under the “LOG IN” button on

www.renesas.com. Some downloads require an additional step to complete a request form that appears when the link is clicked.

If additional support is needed for downloading, contact Renesas via the contact information on the last page.

13. Glossary

Term

Description

ADC

Analog-to-Digital Converter

AI

Artificial Intelligence

CDM

Charged Device Model

CM

Common Mode Generator

HBM

Human Body Model

Indoor Air Quality algorithm using traditional computing methods (legacy)

Indoor Air Quality algorithm using machine learning AI

LGA

Land Grid Array

LV

Low Voltage

MOx

Metal Oxide

MSL

Moisture Sensitivity Level

Mux

Multiplexer

n.a.

Not Applicable