10.7.4

LLC ZCD comparator

The LLC ZCD comparator detects the LLC current zero-crossing during the normal operation to implement the

time-shift control and the anti capacitive protection.

Its output communicates to the LLC SMED.

10.7.5

LLC_FB voltage reading: OPTO feedback loop error

The LLC_FB pin is connected to the optocoupler and its voltage is the error signal of the LLC loop.

The LLC_FB voltage is sampled by the ADC to calculate the time-shift.

10.7.6

Shutdown feature

If the LLC_FB pin is forced below 125 mV, the device shuts down. If the voltage returns over such threshold the

system restarts performing the soft-start.

This feature can be enabled / disabled using a NVM bit.

10.7.7

Algorithm

The LLC operation is based on “Symmetric Time-Shift Control” (STSC), an improved version of time-shift control

that guarantees 50% of the HB duty cycle. The time-shift value is calculated from the LLC_FB pin.

10.8

LLC protections

10.8.1

Anti-capacitive protection

Anti-capacitive control is applied at the SMEDs level using ZCD time events.

The IC monitors the phase relationship between the LLC tank current sensed on the LLC_CS pin and the voltage

at the HVG and LVG, checking the time between the gate rising edge and the tank current zero cross detection.

If this time is below a programmable threshold, which is indicative of impending the capacitive-mode operation,

the monitoring circuit activates the “Soft” ACP procedure: the time-shift is reduced (and therefore the switching

frequency is increased) in order to keep the converter away from that dangerous condition.

If the time reaches “zero” the device is stopped immediately. This is called “Hard” ACP. Both hard and soft ACP

can be enabled and disabled through NVM.

10.8.2

LLC OLP

If the LLC OC1 comparator is triggered the system could enter the overload protection (OLP). STNRG011A is

able to manage two OLP behaviours: time based and frequency based. If the frequency based management is

selected, in case LLC OC1 comparator is triggered the device increases the frequency of the LLC, and if the

maximum OLP occurrence (programmable value) is reached the device is shut down enetering the OLP fault

state that can be programmed as latched or not latched. If the time based management is selected, once the OC1

threshold is triggered the system checks for a programmable time if the OCP1 event is still present, in this case

the device is shut down entering the OLP fault state that can be programmed as latched or not latched.

10.8.3

LLC OCP2

If the LLC OC2 comparator is triggered for a number of times greater than a threshold set by the user the device

sets the OCP2 fault and it is shut down. The OCP2 fault can be programmed as latched or not latched.

10.8.4

LLC soft-start timeout

If the LLC output voltage cannot reach the regulation value within 100 ms, the device enters the LLC soft-start

timeout fault and it is shut down. The fault can be programmed as latched or not latched.

10.8.5

LLC OVP

If the LLC_AUX pin voltage is higher than the LLC OVP comparator threshold (2.5 V), the system enters the LLC

OVP fault state and it is turned off. The fault can be programmed as latched or not latched and can be disabled.

10.8.6

LLC_CS disconnection

If the LLC_CS pin is stuck at 0 V or 5 V during the soft-start the system enters the LLC_CS disconnection fault

(latched) and it is shut down if the disconnection faults detection is enabled in NVM.

STNRG011A

LLC protections

DS13973 - Rev 2

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