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R5F51406BDFM Datasheet(PDF) 82 Page - Renesas Technology Corp

Part # R5F51406BDFM
Description  48-MHz, 32-bit RX MCUs, on-chip FPU, 204 Coremark, up to 256-KB flash memory, up to 36 pins capacitive touch sensing unit, up to 9 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply, Encryption functions (optional)
PDF  118 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F51406BDFM Datasheet(HTML) 82 Page - Renesas Technology Corp

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R01DS0379EJ0110 Rev.1.10
Page 82 of 118
Apr 20, 2022
RX140 Group
2. Electrical Characteristics
2.5.5.8
A/D Converter Trigger
Note 1. tPcyc: PCLK cycle
Figure 2.52
A/D Converter External Trigger Input Timing
2.5.5.9
CAC
Note 1. tPcyc: PCLK cycle
Note 2. tcac: CAC count clock source cycle
Table 2.55
A/D Converter Trigger Timing
Conditions: 1.8 V
≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T
a = –40 to +105°C
Output load conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
A/D converter Trigger input pulse width
tTRGW
1.5
—
tPcyc Figure 2.52
Table 2.56
CAC Timing
Conditions: 1.8 V
≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T
a = –40 to +105°C
Output load conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
Item
Symbol
Min.
Max.
Unit
*1
Test
Conditions
CAC
CACREF input pulse width
tPcyc ≤ tcac*2
tCACREF 4.5 tcac + 3 tPcyc
—ns
tPcyc > tcac*2
5 tcac + 6.5 tPcyc
CACREF input rise/fall time
tCACREFr,
tCACREFf
—
0.1
µs/V
ADTRG0#
PCLK
tTRGW



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