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STM32F407IG Datasheet(PDF) 148 Page - STMicroelectronics |
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STM32F407IG Datasheet(HTML) 148 Page - STMicroelectronics |
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148 / 201 page ![]() Electrical characteristics STM32F405xx, STM32F407xx 148/201 DocID022152 Rev 6 Figure 59. Synchronous multiplexed PSRAM write timings th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization. Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK -ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL- NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) |
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