ADC14L040 datasheet(21/23 Pages) NSC

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Applications Information (Continued)

5.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-

sential to ensure accurate conversion. Maintaining separate

analog and digital areas of the board, with the ADC14L040

between these areas, is required to achieve specified per-

formance.

The ground return for the data outputs (DR GND) carries the

ground current for the output drivers. The output current can

exhibit high transients that could add noise to the conversion

process. To prevent this from happening, the DR GND pins

should NOT be connected to system ground in close prox-

imity to any of the ADC14L040’s other ground pins.

Capacitive coupling between the typically noisy digital cir-

cuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry

separated from the digital circuitry, and to keep the clock line

as short as possible.

Digital circuits create substantial supply and ground current

transients. The logic noise thus generated could have sig-

nificant impact upon system noise performance. The best

logic family to use in systems with A/D converters is one

which employs non-saturating transistor designs, or has low

noise characteristics, such as the 74LS, 74HC(T) and

74AC(T)Q families. The worst noise generators are logic

families that draw the largest supply current transients dur-

ing clock or signal edges, like the 74F and the 74AC(T)

families.

The effects of the noise generated from the ADC output

switching can be minimized through the use of 33

Ω resistors

in series with each data output line. Locate these resistors as

close to the ADC output pins as possible.

Since digital switching transients are composed largely of

high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise.

This is because of the skin effect. Total surface area is more

important than is total ground plane area.

Generally, analog and digital lines should cross each other at

90˚ to avoid crosstalk. To maximize accuracy in high speed,

high resolution systems, however, avoid crossing analog and

digital lines altogether. It is important to keep clock lines as

short as possible and isolated from ALL other lines, including

other digital lines. Even the generally accepted 90˚ crossing

should be avoided with the clock line as even a little coupling

can cause problems at high frequencies. This is because

other lines can introduce jitter into the clock line, which can

lead to degradation of SNR. Also, the high speed clock can

introduce noise into the analog chain.

Best performance at high frequencies and at high resolution

is obtained with a straight signal path. That is, the signal path

through all components should form a straight line wherever

possible.

Be especially careful with the layout of inductors. Mutual

inductance can change the characteristics of the circuit in

which they are used. Inductors should not be placed side by

side, even with just a small part of their bodies beside each

other.

The analog input should be isolated from noisy signal traces

to avoid coupling of spurious signals into the input. Any

external component (e.g., a filter capacitor) connected be-

tween the converter’s input pins and ground or to the refer-

ence input pin and ground should be connected to a very

clean point in the ground plane.

All analog circuitry (input amplifiers, filters, reference com-

ponents, etc.) should be placed in the analog area of the

board. All digital circuitry and I/O lines should be placed in

the digital area of the board. The ADC14L040 should be

between these two areas. Furthermore, all components in

the reference circuitry and the input signal chain that are

connected to ground should be connected together with

short traces and enter the ground plane at a single, quiet

point. All ground connections should have a low inductance

path to ground.

6.0 DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source

driving the CLK input must be free of jitter. Isolate the ADC

clock from any digital circuitry with buffers, as with the clock

tree shown in Figure 6. The gates used in the clock tree must

be capable of operating at frequencies much higher than

those used if added jitter is to be prevented.

Best performance will be obtained with a differential input

drive, compared with a single-ended drive, as discussed in

Sections 1.3.1 and 1.3.2.

As mentioned in Section 5.0, it is good practice to keep the

ADC clock line as short as possible and to keep it well away

from any other signals. Other signals can introduce jitter into

the clock signal, which can lead to reduced SNR perfor-

mance, and the clock can introduce noise into other lines.

Even lines with 90˚ crossings have capacitive coupling, so

try to avoid even these 90˚ crossings of the clock line.

7.0 COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, all inputs should not go

more than 100 mV beyond the supply rails (more than

100 mV below the ground pins or 100 mV above the supply

pins). Exceeding these limits on even a transient basis may

cause faulty or erratic operation. It is not uncommon for high

speed digital components (e.g., 74F and 74AC devices) to

exhibit overshoot or undershoot that goes above the power

supply or below ground. A resistor of about 47

Ω to 100Ω in

series with any offending digital input, close to the signal

source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage,

even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC14L040 with

a device that is powered from supplies outside the range of

the ADC14L040 supply. Such practice may lead to conver-

sion inaccuracies and even to device damage.

20146517

FIGURE 6. Isolating the ADC Clock from other Circuitry

with a Clock Tree

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