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IT8712F V0.81
ii
Contents
CONTENTS
1. Features
................................................................................................................................................ 1
2. General Description ....................................................................................................................................... 3
3. Block Diagram................................................................................................................................................ 5
4. Pin Configuration............................................................................................................................................ 7
5. IT8712F Pin Descriptions............................................................................................................................... 9
6. List of GPIO Pins ......................................................................................................................................... 21
7. Power On Strapping Options and Special Pin Routings .............................................................................. 23
8. Configuration .............................................................................................................................................. 25
8.1
Configuring Sequence Description.................................................................................................... 25
8.2
Description of the Configuration Registers........................................................................................ 27
8.2.1
Logical Device Base Address............................................................................................... 32
8.3
Global Configuration Registers (LDN: All)......................................................................................... 34
8.3.1
Configure Control (Index=02h) ............................................................................................. 34
8.3.2
Logical Device Number (LDN, Index=07h)........................................................................... 34
8.3.3
Chip ID Byte 1 (Index=20h, Default=87h)............................................................................. 34
8.3.4
Chip ID Byte 2 (Index=21h, Default=12h)............................................................................. 34
8.3.5
Configuration Select and Chip Version (Index=22h, Default=07h)....................................... 34
8.3.6
Clock Selection Register (Index=23h, Default=00h) ............................................................ 34
8.3.7
Software Suspend (Index=24h, Default=00h, MB PnP) ....................................................... 35
8.3.8
GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h) ..................... 35
8.3.9
GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) ..................... 36
8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) ..................... 36
8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h) ..................... 37
8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h) ..................... 37
8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h) ..................... 38
8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h) ....................................................... 39
8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh)..................... 39
8.3.16 Test 1 Register (Index=2Eh, Default=00h) ........................................................................... 40
8.3.17 Test 2 Register (Index=2Fh, Default=00h) ........................................................................... 40
8.4
FDC Configuration Registers (LDN=00h) ......................................................................................... 41
8.4.1
FDC Activate (Index=30h, Default=00h)............................................................................... 41
8.4.2
FDC Base Address MSB Register (Index=60h, Default=03h).............................................. 41
8.4.3
FDC Base Address LSB Register (Index=61h, Default=F0h) .............................................. 41
8.4.4
FDC Interrupt Level Select (Index=70h, Default=06h) ......................................................... 41
8.4.5
FDC DMA Channel Select (Index=74h, Default=02h) .......................................................... 41
8.4.6
FDC Special Configuration Register 1 (Index=F0h, Default=00h) ....................................... 41
8.4.7
FDC Special Configuration Register 2 (Index=F1h, Default=00h) ....................................... 42
8.5
Serial Port 1 Configuration Registers (LDN=01h) ............................................................................. 43
8.5.1
Serial Port 1 Activate (Index=30h, Default=00h) .................................................................. 43
8.5.2
Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) ................................... 43
8.5.3
Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) .................................... 43
8.5.4
Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) ............................................. 43
8.5.5
Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h) ........................... 43
8.5.6
Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h) ........................... 44
8.5.7
Serial Port 1 Special Configuration Register 3 (Index=F2h, Default=00h) ........................... 44
8.5.8
Serial Port 1 Special Configuration Register 4 (Index=F3h, Default=7Fh) ........................... 44
8.6
Serial Port 2 Configuration Registers (LDN=02h) ............................................................................. 45
8.6.1
Serial Port 2 Activate (Index=30h, Default=00h) .................................................................. 45
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