MC33780 datasheet(21/37 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33780

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

--------------------------------------------------------------------------

-- Calculates the 4-bit CRC (x^4 + 1) serially for 8 to 16 bits of data.

--------------------------------------------------------------------------

constant CRCPoly: std_logic_vector: = “0001”; -- x^4 +1

constant InitCrc: std_logic_vector: = “1010”;

procedure SerialCalculateCRC4(CRC: input std_logic_vector;Data: in std_logic) is variable

Xor1:

std_logic;

begin

Xor1: = CRC(3) xor Data;

CRC: = CRC(2 downto 0) & ‘0’; -- Shift left 1 bit

if Xor1 = ‘1’ then

CRC: = CRC xor CRCPoly

end if;

end SerialCalculateCRC4;

Figure 16. CRC Algorithm

Figure 17. Default CRC Block Diagram

MESSAGE SIZE SPECIAL CASES

The response to any 8- to 15-bit message is expected to

be another 8- to 15-bit message and the response to any

16-bit message is expected to be another 16-bit message.

This gives rise to some special cases when there is a

transition from one message size to a different message size.

Some messages must be long words (16 bits of data), others

can be short words (8 to 15 bits of data).

The following are examples where the word is a standard

DSI formatted short word (8 bits of data and 4 bits of CRC).

Example 1: If the previous message was a short word and

the current message is a long word, the response message

(which is also a short word) finishes before the current

message frame and the CRC bits look like data bits in the

long word format. Since the CRC validation of this short word

message response is not reliable, this short word response

should not be used.

Example 2: If the previous message was a long word and

the current message is a short word, the response message

(which is also a long word) cannot finish before the current

message frame. Bits three to zero of the data and the CRC

bits are lost. Data bits seven to four of the 16-bit response

message look like the CRC bits of an 8-bit response and

almost certainly would not be correct. Because the response

is incomplete and the CRC check is probably not valid, this

response is not useful.

The long word to short word message size transition

normally only occurs after setting up the DBUS peripherals.

During address setup, a message with address 0000 is sent

to attempt to set the address of the next peripheral on the

daisy-chained bus. Before any peripherals have been

assigned an address, their bus switches are opened so the

addressing message only goes to the first peripheral in line.

As each peripheral gets an address, it closes its bus switch

so the next address assignment command can reach the next

peripheral in line on the bus. Each peripheral responds to an

address assignment only once (during the next message

after the command that set its address). After the last

peripheral has been assigned an address, any subsequent

address assignments will receive no response. When the

master MCU fails to receive a response, it knows it has

passed the last peripheral. At this point, short word messages

may be sent. The first such message will have no meaningful

response associated with it.

The first message after reset is also a special case

because there was no previous message, therefore there will

be no meaningful response during the first message transfer.

Input Data

1X4

0X3

0X2

0X1

+X0

= X4+1

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