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AM6548 Datasheet(PDF) 224 Page - Texas Instruments |
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AM6548 Datasheet(HTML) 224 Page - Texas Instruments |
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224 / 284 page  7.9.5.18.2.1 OSPI Timing Requirements - SDR Mode Table 7-67. OSPI DLL Delay Mapping - SDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE All modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x0 PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 see Figure 7-86 and Figure 7-87 NO. MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge(1) 1.8V, Internal Loopback -2.18 ns 3.3V, Internal Loopback -1.7 ns O20 th(CLK-D) Hold time, D[i:0] valid after active CLK edge(1) 1.8V, Internal Loopback 7.62 ns 3.3V, Internal Loopback 8.1 ns O21 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback -3.24 ns 3.3V, External Board Loopback -2.72 ns O22 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback 3.81 ns 3.3V, External Board Loopback 4.33 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 7-86. OSPI Timing Requirements - SDR, Internal Clock and Internal Pad Loopback Clock OSPI_DQS OSPI_D[i:0] OSPI_TIMING_06 O21 O 2 2 Figure 7-87. OSPI Timing Requirements - SDR, External Loopback Clock 7.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode NO. DESCRIPTION(1) MODE MIN MAX UNIT O7 tc(CLK) Cycle time, CLK 1.8V 7 ns 3.3V 7.52 ns O8 tw(CLKL) Pulse duration, CLK low -0.3+0.475×P (1) ns O9 tw(CLKH) Pulse duration, CLK high -0.3+0.475×P (1) ns AM6548, AM6528, AM6546, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 www.ti.com 224 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6548 AM6528 AM6546 AM6526 |
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