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OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_01

OSPI_CSn

Figure 7-90. OSPI Switching Characteristics - DDR

For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM.

7.9.5.19 OLDI

7.9.5.19.1 OLDI Switching Characteristics

NO.

PARAME

TER

DESCRIPTION(1)

MIN

TYP

MAX

UNIT

OLDI1

tt(LHTT)

Low-to-high transition time of LVDS differential signals:

OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0

(Fast rise/fall disabled)

0.5

Low-to-high transition time of LVDS differential signals:

OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1

(Fast rise/fall enabled)

0.25

OLDI2

tt(HLTT)

High-to-low transition time of LVDS differential signals:

OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0

(Fast rise/fall disabled)

0.5

High-to-low transition time of LVDS differential signals:

OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1

(Fast rise/fall enabled)

0.25

OLDI3

tc(CLK)

Output pixel clock period (OLDI0_CLKP/N)

6.06

110.01

OLDI4

tw(BIT)

Output bit width (OLDI0_AxP/N, x = [3:0])

UI(2)

OLDI5

t(TPPx,

x=[6:0])

Output pulse positions normalized for each bit (OLDI0_AxP/N, x =

[3:0])

7-1

UI(2)

OLDI6

Δt(TPP)

Variation of pulse positions for each bit from their normalized center

(OLDI0_AxP/N, x = [3:0])

0.1

UI(2)

OLDI7

tsk(TCCS)

Output channel to channel skew (OLDI0_CLKP/N, OLDI0_AxP/N, x

= [3:0])

OLDI8

tj(TJCC)

Output jitter cycle-to-cycle (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0])

0.04

UI(2)

OLDI9

tj(IJIT)

Total jitter tolerance (Includes data to clock skew, pulse position

variation from normalized edges (OLDI0_AxP/N, x = [3:0])

0.25

UI(2)

(1)

Measured based on 20% - 80% transitions and PCB trace of ~2in with 100 Ω termination on differential lines.

(2)

UI = tc(CLK) / 7

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AM6548, AM6528, AM6546, AM6526

SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021

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