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AM6548 Datasheet(PDF) 247 Page - Texas Instruments |
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AM6548 Datasheet(HTML) 247 Page - Texas Instruments |
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247 / 284 page  7.9.5.25.2.1 JTAG Electrical Data and Timing Section 7.9.5.25.2.1.1, Section 7.9.5.25.2.1.2, and Figure 7-125 assume testing over the recommended operating conditions and electrical characteristic conditions. 7.9.5.25.2.1.1 JTAG Timing Requirements NO. PARAMETER DESCRIPTION MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 60 ns J2 tw(TCKH) Pulse width minimum, TCK high 24 ns J3 tw(TCKL) Pulse width minimum, TCK low 24 ns J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 7 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 7 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 4 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 4 ns 7.9.5.25.2.1.2 JTAG Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 24 ns TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 Figure 7-125. JTAG Test-Port Timing www.ti.com AM6548, AM6528, AM6546, AM6526 SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 247 Product Folder Links: AM6548 AM6528 AM6546 AM6526 |
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