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L9780 Datasheet(PDF) 51 Page - STMicroelectronics |
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L9780 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 56 page ![]() DocID026356 Rev 3 51/56 L9780 Electrical characteristics 55 SPI data shift happens on rising edges. Logic timing parameters are defined in Figure 11. Figure 11. SPI timing diagram Table 18. Logic communications timing Parameter Conditions Min. Max. Unit Transfer frequency (ft) - - 8 MHz CLK period (tCLK) - 125 - ns Enable lead time (tenLEAD) - 375 - Enable lag time (tenLAG) - 50 - CLK high time (tCLKH) - 50 - CLK low time (tCLKL) - 50 - SI input setup time (tSIS) - 15 - SI input hold time (tSIH) - 20 SO access time (tSOA) VCCI = 3.13 V; Cload = 50 pF - 340 VCCI = 3.13 V; Cload = 100 pF VCCI = 4.75 V; Cload = 50 pF VCCI = 4.75 V; Cload = 100 pF SO disable time (tSOD) - - 100 SO output valid time (tSOV) VCCI = 3.13 V; Cload = 50 pF - 60 VCCI = 3.13 V; Cload = 100 pF - 160 VCCI = 4.75 V; Cload = 50 pF - 40 VCCI = 4.75 V; Cload = 100 pF - 80 SO output hold time (tSOH) - 20 - CLK hold time (tCLKHOLD) - 300 - CSN negated time (tCSN) - 2 - μs |
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