3.11

GPIO

There are 34 GPIOs in this device.

The GPIO block provides programmable inputs or outputs. Each input or output can be controlled in two modes:

•

Software mode through an APB bus interface

•

Alternate function mode, where GPIO becomes a peripheral input or output line

Any GPIO input can be independently enabled or disabled (masked) for interrupt generation. User can select for

each GPIO which edge (rising, falling, both) will trigger an interrupt.

A de-bouncing logic can be enabled for each GPIO to filter glitches on IOs before going to the Interrupt generation

and CPU read value.

All GPIOs are fail safe to avoid leakage consumption in any condition even when the ring is off and the external

line is logic level high.

3.12

Multi Timer Unit (MTU)

Multi Timer Unit consists of eight timers. Each timer is clocked by MXTAL frequency divided by 8 (which means

2.4 MHz with a 19.2 MHz crystal) or REFCLK (32.768 kHz) inputs.

3.12.1

MTU feature overview

•

The Multi Timer Unit provides access to four interrupt generating programmable 32-bit Free-Running

decrementing Counters (FRCs) allowing up to four counts to be performed in parallel.

•

The FRCs have their own clock input, allowing the counters to run from a much slower clock than the system

clock.

•

In each FRC the 32-bit counter is split up into two 16-bit counters.

3.13

RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 256 bytes SRAM and supplied

with a dedicated voltage regulator.

The RTC provides a high resolution clock which can be used for GPS. It keeps the time when the system is

inactive and can be used to wake up the system when a programmed alarm time is reached. It has a clock

trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update.

RTC features:

•

47-bit counter clocked by 32.768 kHz clock

•

32-bit for the integer part (seconds) and 15-bit for the fractional part

•

The integer part and the fractional part are readable independently

•

The counter, once enabled, can be stopped

•

Integer part load register (32-bit)

•

Fractional part load register (15-bit)

•

Load bit to transfer the content of the entire load register (integer + fractional part) to the 47-bit counter

Once set by the MCU this bit is cleared by the hardware to signal to the MCU that the RTC has been updated.

3.14

MSP

STA8135GA has one Multi mode Serial Port (MSP).

The following section describes the functionalities of the MSP unit.

The Multi mode Serial Port (MSP) is a synchronous transmitter serial interface.

The MSP provides:

•

Element (data) sizes of 8, 10, 12, 14, 16, 20, 24, and 32 bits, LSB or MSB first

•

Programmable frequency shift clock for data transfer

•

Direct interface to SPI compliant devices

•

Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep

STA8135GA

GPIO

DB4575 - Rev 1

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