L9177A datasheet(36/55 Pages) STMICROELECTRONICS

36 / 55 page

Figure 29. VRS interface structure

GAPGPS00612

VRS voltage

Int_vrs

Auto adaptative

Hysteresis

Auto adaptative

Time filtering block

Out_vrs

3.6.2

Auto-adaptative hysteresis

Input signals difference is obtained through a full differential amplifier; its output, DV signal, is fed to peak

detection circuit and then to A/D converter implemented with 4 voltage comparator (5 levels Pvi).Output of A/D is

sent to Logic block (hysteresis selection Table 32) that implements correlation function between Peak voltage and

hysteresis value; hysteresis value is used by square filtering circuit which conditions DV signal.

Figure 30. Auto-adaptive hysteresis block diagram

GAPGPS00613

PVi

VRS voltage

Hysteresis Squarer Circuit and

Temporal Filtering

Hysteresis

Value

Hysteresis

Selection

Table

Peak Detection

Circuit

AD converter

–

Int_vrs

Figure 31. Hysteresis output voltage level

GAPGPS00614

Hysteresis output

voltage (mV)

Quantized peak detector

output voltage (mV)

PV1

PV2

PV3

PV4

To the previous 5 levels PV = [0 PV1 PV2 PV3 PV4] correspond to a set of 5 thresholds:

•

H = [HO HIH2 H3 H4]

The advised values for the previous defined vectors are:

•

PV = [0 PV1 PV2 PV3 PV4] = [0, 900, 1560, 2230, 2900] mV

•

H = [H0 H1 H2 H3 H4] = [100, 200, 350, 650, 1000] mV

L9177A

VRS interface

DS12175 - Rev 5

page 36/55

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