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LSM6DSV16BX Datasheet(PDF) 28 Page - STMicroelectronics |
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LSM6DSV16BX Datasheet(HTML) 28 Page - STMicroelectronics |
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28 / 148 page  Command Command code Default Description GETPID 0x8D 0x02 0x08 0x00 0x71 0x92 0x0B SDO = 1 0x02 0x08 0x00 0x71 0x12 0x0B SDO = 0 GETBCR 0x8E 0x27 (1 byte) Bus characteristics register GETDCR 0x8F 0x44 default MIPI I3C® device characteristics register GETSTATUS 0x90 0x00 0x00 (2 byte) Status register GETMXDS 0x94 0x08 0x60 Return max write and read speed GETCAPS 0x95 0x00 0x11 0x18 0x00 Provide information about device capabilities and supported extended features SETGRPA 0x9B Group address assignment command RSTGRPA 0x2C / 0x9C Reset the group address RSTACT 0x9A / 0x2A Configure slave reset action 5.2.3 Overview of anti-spike filter management The device acts as a standard I²C target as long as it has an I²C static address. The device is capable of detecting and disabling the I²C anti-spike filter after detecting the broadcast address (7'h7E/W). In order to guarantee proper behavior of the device, the I3C master must emit the first START, 7'h7E/W at open-drain speed using I²C fast mode plus reference timing. After detecting the broadcast address, the device can receive the I3C dynamic address following the I3C push- pull timing. If the device is not assigned a dynamic address, then the device will continue to operate as an I²C device with no anti-spike filter. For the case in which the host decides to keep the device as I²C with anti-spike filter, there is a configuration required to keep the anti-spike filter active. This configuration is done by writing the ASF_CTRL bit to 1 in the IF_CFG (03h) register. This configuration forces the anti-spike filter to always be turned on instead of being managed by the communication on the bus. LSM6DSV16BX MIPI I3C® interface DS13771 - Rev 2 page 28/148 |
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