7
COMMAND REGISTER
The Command Register controls specific modes and
functions
7
6
5
4
3
2
1
0
PMC
TIC
PMC1
PMC0
PME
REM
TIC1
TIC0
IRD
DTR
Bits 7-6
Parity Mode Control (PMC)
7
6
0
0
Odd parity transmitted/received
0
1
Even parity transmitted/received
1
0
Mark parity bit transmitted
Parity check disabled
1
1
Space parity bit transmitted
Parity check disabled
Bit 5
Parity Mode Enabled (PME)
0
Parity mode disabled
No parity bit generated
Parity check disabled
1
Parity mode enabled
Bit 4
Receiver Echo Mode (REM)
0
Receiver normal mode
1
Receiver echo mode bits 2 and 3
Must be zero for receiver echo
mode, RTS will be low
Bit 1
Receiver Interrupt Request Disabled (IRD)
0
IRQB enabled
1
IRQB disabled
Bit 0
Data Terminal Ready (DTR)
0
Data terminal not ready (DTRB high)
1
Data terminal ready (DTRB low)
Reset Initialization
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Hardware reset (RESB)
-
-
-
0
0
0
0
0
Program reset
Data Terminal Ready (Bit 0)
This bit enables all selected interrupts and controls the state
of the Data Terminal Ready (DTRB) line. A 0 indicates the
microcomputer system is not ready by setting the DTRB line
high. A 1 indicates the microcomputer system is ready by
setting the DTRB line low.
Receiver Interrupt Control (Bit 1)
This bit disables the Receiver from generating an interrupt
when set to a 1. The Receiver interrupt is enabled when this
bit is set to a 0 and Bit 0 is set to a 1.
Transmitter Interrupt Control (Bits 2, 3)
These bits control the state of the Ready to Send (RTSB) line
and the Transmitter interrupt.
Receiver Echo Mode (Bit 4)
A 1 enables the Receiver Echo Mode and a 0 enables the
Receiver Echo Mode. When bit 4 is a 1 bits 2 and 3 must be
0. In the Receiver Echo Mode, the Transmitter returns each
transmission received by the Receiver delayed by one-half bit
time.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A 0
disables parity bit generation by the Transmitter and parity
bit checking by the Receiver. A 1 bit enables generation and
checking of parity bits.
Parity Mode Control (Bits 6, 7)
These bits determine the type of parity generated by the
Transmitter (even, odd, mark or space) and the type of parity
check done by the Receiver (even, odd or no check).
Bits 3-2
Transmitter Interrupt Control (TIC)
3
2
0
0
RTSB = High, transmit interrupt disabled
0
1
RTSB = Low, transmit interrupt enabled
1
0
RTSB = Low, transmit interrupt disabled
1
1
RTSB = Low, transmit interrupt disabled
Transmit break on TxD
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