MPC9351

MOTOROLA

TIMING SOLUTIONS

8

target this range. The key parameter that needs to be met in

the final filter design is the DC voltage drop across the series

filter resistor RF. From the data sheet the ICCA current (the

current sourced through the VCCA pin) is typically 3 mA (5 mA

maximum), assuming that a minimum of 2.325V (VCC=3.3V

or VCC=2.5V) must be maintained on the VCCA pin. The

resistor RF shown in Figure 6. “VCCA Power Supply Filter”

must have a resistance of 270

W (VCC=3.3V) or 9-10W

(VCC=2.5V) to meet the voltage drop criteria.

Figure 6. VCCA Power Supply Filter

VCCA

VCC

MPC9351

10 nF

RF = 270Ω for VCC = 3.3V

RF = 9–10Ω for VCC = 2.5V

CF

33...100 nF

RF

VCC

CF = 1 µF for VCC = 3.3V

CF = 22 µF for VCC = 2.5V

The minimum values for RF and the and the filter capacitor

CF are defined by the required filter characteristics: the RC

filter should provide an attenuation greater than 40 dB for

noise whose spectral content is above 100 kHz. In the

example RC filter shown in Figure 6. “VCCA Power Supply

Filter”, the filter cut-off frequency is around 3-5 kHz and the

noise attenuation at 100 kHz is better than 42 dB.

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL. Although the MPC9351 has

several design features to minimize the susceptibility to

power supply noise (isolated power and grounds and fully

differential PLL) there still may be applications in which

overall performance is being degraded due to system power

supply noise. The power supply filter schemes discussed in

this section should be adequate to eliminate power supply

noise related problems in most designs.

Driving Transmission Lines

The MPC9351 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to Motorola application note

AN1091. In most high performance clock networks

point-to-point distribution of signals is the method of choice.

In a point-to-point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50

Ω resistance to VCC÷2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9351 clock driver. For the series terminated

case however there is no DC current draw, thus the outputs

can drive multiple series terminated lines. Figure 7. “Single

versus Dual Transmission Lines” illustrates an output driving

a single series terminated line versus two series terminated

lines in parallel. When taken to its extreme the fanout of the

MPC9351 clock driver is effectively doubled due to its

capability to drive multiple lines.

Figure 7. Single versus Dual Transmission Lines

14

Ω

IN

MPC9351

OUTPUT

BUFFER

RS = 36Ω

ZO = 50Ω

OutA

14

Ω

IN

MPC9351

OUTPUT

BUFFER

RS = 36Ω

ZO = 50Ω

OutB0

RS = 36Ω

ZO = 50Ω

OutB1

The waveform plots in Figure 8. “Single versus Dual Line

Termination Waveforms” show the simulation results of an

output driving a single line versus two lines. In both cases the

drive capability of the MPC9351 output buffer is more than

sufficient to drive 50

Ω transmission lines on the incident

edge. Note from the delay measurements in the simulations a

delta of only 43ps exists between the two differently loaded

outputs. This suggests that the dual line driving need not be

used exclusively to maintain the tight output-to-output skew

of the MPC9351. The output waveform in Figure 8. “Single

versus Dual Line Termination Waveforms” shows a step in

the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 36

Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Z0 ÷ (RS+R0 +Z0))

Z0 = 50Ω || 50Ω

RS = 36Ω || 36Ω

R0 = 14Ω

VL = 3.0 ( 25 ÷ (18+17+25)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.6V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

Freescale Semiconductor, Inc.

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