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GD25Q21B Datasheet(PDF) 27 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q21B Datasheet(HTML) 27 Page - GigaDevice Semiconductor (Beijing) Inc. |
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27 / 51 page ![]() Uniform Sector Dual and Quad Serial Flash GD25Q21B 27 the last data byte has been latched in; otherwise the Page Program command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) is not executed. Figure 19. Page Program Sequence Diagram Command 0 1 2 3 4 5 6 7 02H CS# SCLK SI 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24-bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 CS# SCLK SI MSB Data Byte 2 32 33 34 35 7 6 5 4 3 2 1 0 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 Data Byte 1 Data Byte 3 Data Byte 256 MSB MSB MSB 36 37 38 39 |
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