www.statschippac.com

FEATURES

• 2 to 7 die stack with spacer capability

• Flexible body sizes range from 4mm x 4mm to

13mm x 13mm

• Package height at 1.0, 1.2, 1.4mm max

• Flexible die stacking options (“pyramid,” “same die,”

etc.)

• 0.5mm minimum land pitch, flexible land pattern

• Flash/SRAM/PSRAM/Logic/Analog combinations

• JEDEC standard package outlines

• Die thinning to 75um (3mils) capability

• Low loop wire bonding; reverse and die to die

• Up to 2mm die overhang per side

• Halogen-free and Low-K wafer compatible BOM

APPLICATIONS

• Handheld devices

• Wireless RF

• Analog

• ASIC

• Memory

• Simple PLDs

• Stacking of die allows for more functionality

in an array molded, cost effective, space

saving package solution

• Available in 1.2mm (TFLGA), 1.0mm (VFLGA),

and 0.8mm (WFLGA) maximum thickness

• Thinner than FBGA

• Exposed thermal/mechanical lands available

• Laminate substrate based enabling

2 and 4 layers of routing flexibility

DESCRIPTION

STATS ChipPAC’s chip stack technology offers the flexibility

of stacking 2 to 7 die in a single package. Die to die bonding

capability enables device and signal integration to improve

electrical performance and reduce overall package I/O

requirements. Wafer thinning technology, overhang wire

bond technology, and the use of spacers between stacked

die provide the flexibility to stack almost any desirable

configuration of die in one package. This capability uses

existing assembly infrastructure, which results in more

functional integration with lower overall package cost. The

use of the latest packaging materials allows this package to

meet JEDEC Moisture Resistance Test Level 2a with

Lead-free reflow condition. This is an ideal package for cell

phone applications where Digital, Flash, SRAM, PSRAM

and Logic are stacked into a single package.

FLGA-SD

Fine Pitch Land Grid Array - Stacked Die