7

A Product Line of

Diodes Incorporated

PI6CB184Q

www.diodes.com

September 2022

Diodes Incorporated

PI6CB184Q

Document Number DS41705 Rev 4-2

HCSL Input Characteristics

Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions

Symbol Parameters

Conditions

Min.

Typ.

Max.

Units

VIHDIF

Diff. Input High Voltage(3)

IN+, IN-, single-end measurement

600

800

1150

mV

VILDIF

Diff. Input Low Voltage(3)

IN+, IN-, single-end measurement

-300

0

300

mV

VCOM

Diff. Input Common Mode

Voltage

150

1000

mV

VSWING

Diff. Input Swing Voltage

Peak to peak value (VIHDIF - VILDIF)

300

1450

mV

fINBP

Input Frequency

PLL Bypass mode

1

200

MHz

fIN100

Input Frequency

100MHz PLL

60

100

110

MHz

fIN125

Input Frequency

125MHz PLL

75

125

137.5

MHz

fIN156

Input Frequency

50MHz PLL

30

50

65

MHz

tSTAB

Clock Stabilization

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st

clock

0.6

1.0

ms

tRF

Diff. Input Slew Rate(2)

Measured differentially

0.4

V/ns

IIN

Diff. Input Leakage Current

VIN = VDD, VIN = GND

-5

0.01

5

uA

tDC

Diff. Input Duty Cycle

Measured differentially

45

55

%

tjc-c

Diff. Input Cycle to cycle jitter Measured differentially

125

ps

Note:

1. Guaranteed by design and characterization, not 100% tested in production

2. Slew rate measured through +/-75mV window centered around differential zero

3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2

LVCMOS AC Electrical Characteristics

Temperature = TA; Supply voltages per normal operation conditions; See test circuits for the load conditions

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Units

tOELAT

Output enable latency

Q start after OE# assertion

Q stop after OE# deassertion

1

3.5

clocks

tPDLAT

PD# de-assertion

Differential outputs enable after PD# de-

assertion

20

300

us