ST7LUS5 datasheet(50/124 Pages) STMICROELECTRONICS

50 / 124 page

Power saving modes

ST7LUS5, ST7LU05, ST7LU09

50/124

Figure 22.

Halt mode flowchart

WDGHALT is an option bit. See option bytes in Section 14.1.1: Flash configuration for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 15: Interrupt mapping on page 39 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering Halt mode.

Halt mode recommendations

●

Make sure that an external event is available to wake up the microcontroller from Halt

mode.

●

When using an external interrupt to wake up the microcontroller, re-initialize the

corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT

HALT INSTRUCTION

RESET

INTERRUPT(3)

CPU

OSCILLATOR

PERIPHERALS(2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X(4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X(4)

64 CPU CLOCK CYCLE

DELAY(5)

WATCHDOG

ENABLE

DISABLE

WDGHALT(1)

WATCHDOG

RESET

(Active Halt disabled)

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