December 1994

13

Philips Semiconductors

Product specification

256 x 8-bit CMOS EEPROMS

PCX8582X-2 Family

Note

1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be

internally provided by a transmitter.

SYMBOL

PARAMETER

CONDITIONS

MIN. MAX. UNIT

clock frequency

0

100

kHz

time the bus must be free before new transmission can start

4.7

−

µs

start condition hold time after which first clock pulse is generated

4.0

−

µs

LOW level clock period

4.7

−

µs

HIGH level clock period

4.0

−

µs

set-up time for start condition

repeated start

4.7

−

µs

data hold time for bus compatible masters

5

−

µs

data hold time for bus devices

note 1

0

−

ns

data set-up time

250

−

ns

SDA and SCL rise time

−

1

µs

SDA and SCL fall time

−

300

ns

set-up time for stop condition

4.7

−

µs