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STM32H745II Datasheet(PDF) 175 Page - STMicroelectronics |
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STM32H745II Datasheet(HTML) 175 Page - STMicroelectronics |
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175 / 252 page ![]() DS12923 Rev 1 175/252 STM32H745xI/G Electrical characteristics 228 NAND controller waveforms and timings Figure 34 through Figure 37 represent synchronous waveforms, and Table 87 and Table 88 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 • Capacitive load CL = 30 pF In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period. Figure 34. NAND controller waveforms for read access FMC_NWE FMC_NOE (NRE) FMC_D[15:0] tsu(D-NOE) th(NOE-D) MS32767V1 ALE (FMC_A17) CLE (FMC_A16) FMC_NCEx td(ALE-NOE) th(NOE-ALE) |
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