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STM32H753II Datasheet(PDF) 314 Page - STMicroelectronics |
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STM32H753II Datasheet(HTML) 314 Page - STMicroelectronics |
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314 / 361 page ![]() Electrical characteristics (rev V) STM32H753xI 314/360 DS12117 Rev 8 Figure 113. ULPI timing diagram Ethernet interface characteristics Unless otherwise specified, the parameters given in Table 212, Table 213 and Table 214 for SMI, RMII and MII are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 121: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL=20 pF • Measurement points are done at CMOS levels: 0.5VDD • IO Compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS1 Refer to Section 7.3.15: I/O port characteristics for more details on the input/output characteristics: 1. Guaranteed by characterization results. Table 212. Dynamics characteristics: Ethernet MAC signals for SMI (1) 1. Guaranteed by characterization results. Symbol Parameter Min Typ Max Unit tMDC MDC cycle time( 2.5 MHz) 400 400 403 ns Td(MDIO) Write data valid time 0.5 1.5 4 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tHD tSD tHC tSC ai17361c tDC |
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