STM32G483CEH3 datasheet(19/230 Pages) STMICROELECTRONICS

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DS12997 Rev 4

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STM32G483xE

Functional overview

3.5

Embedded SRAM

STM32G483xE devices feature 128 Kbytes of embedded SRAM. This SRAM is split into

three blocks:

•

80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the

SRAM1 through the System Bus or through the I-Code/D-Code buses. The first

32 Kbytes of SRAM1 support hardware parity check.

•

16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the

SRAM2 through the System bus. SRAM2 can be retained in standby modes.

•

32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU

through I-Code/D-Code bus for maximum performance.

It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,

DMA2) through SBUS contiguously to SRAM1 and SRAM2. The CCM SRAM supports

hardware parity check and can be write-protected with 1-Kbyte granularity.

•

The memory can be accessed in read/write at max CPU clock speed with 0 wait states.

3.6

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, FSMC, QUADSPI, AHB and APB peripherals). It also ensures a

seamless and efficient operation even when several high-speed peripherals work

simultaneously.

Figure 2. Multi-AHB bus matrix

MSv42663V1

Cortex

®-M4

with FPU

DMA1

DMA2

FSMC

AHB2

peripherals

AHB1

peripherals

CCM

SRAM

SRAM1

FLASH

512 KB

ICode

DCode

BusMatrix-S

SRAM2

QUADSPI

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