MPC8540 datasheet(313/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-9

L2INTDIS

Cache read intervention disable. Reserved for full memory-mapped SRAM mode. Used to disable

cache read intervention. May be changed while the L2 is enabled or disabled.

0 Cache intervention is enabled. The ECM ensures that if a data read from another device hits in

the L2 cache, it is serviced from the L2 cache.

1 Cache intervention is disabled

13–15

L2SRAM

L2 block assignment. Determines the L2 cache/memory-mapped SRAM block assignment.

L2SIZ = L2BLKSIZ (1 block):

000 Block 0 = Cache

001 Block 0 = SRAM0

010–111 Reserved

L2SIZ = L2BLKSIZ

× 2 (2 blocks):

Block 0

Block 1

000 Unused

Cache

001 SRAM0

Unused

010 SRAM0

Cache

011 SRAM0

SRAM1

1xx Reserved

To change these bits, the L2 must be disabled (L2CTL[L2E] = 0).

16–17

—

Reserved

L2LO

L2 cache lock overflow. Reserved in full memory-mapped SRAM mode. This sticky bit is set if an

overlock condition is detected in the L2 cache. A lock overflow is triggered either by executing

instruction or data cache block touch and lock set instructions or by performing L2 cache external

writes with lock set. If all ways are locked and an attempt to stash is made, the stash is not

allocated.

0 The L2 cache did not encounter a lock overflow. L2LO is cleared only by software.

1 The L2 cache encountered a lock overflow condition.

L2SLC

L2 snoop lock clear. This sticky bit is set if a snoop invalidated a locked data cache line. Note that

the lock bit for that line is cleared whenever the line is invalidated. L2SLC is reserved in full

memory-mapped SRAM mode.

0 A snoop did not invalidate a locked L2 cache line. L2SLC is cleared only by software.

1 The L2 cache encountered a snoop that invalidated a locked line.

—

Reserved

L2LFR

L2 cache lock bits flash reset. The L2 cache must be enabled (L2CTL[L2E] = 1) for reset to occur.

This field is reserved in full memory-mapped SRAM mode.

0 The L2 cache lock bits are not cleared or the clear operation completed.

1 A reset operation is issued that clears each L2 cache line’s lock bits. Depending on the L2LFRID

value, data or instruction locks, or both can be reset. Cache access is blocked during this time.

After L2LFR is set, the L2 cache unit automatically clears L2LFR when the reset operation is

complete (if L2CTL[L2E] is set).

22–23

L2LFRID

L2 cache lock bits flash reset select instruction or data. Indicates whether data or instruction lock

bits or both are reset.

00 Not used

01 Reset data locks if L2LFR = 1

10 Reset instruction locks if L2LFR = 1

11 Reset both data and instruction locks if L2LFR = 1

24–31

—

Reserved

Table 7-2. L2CTL Field Descriptions (continued)

Bits

Name

Description

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