MPC8540 datasheet(310/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-6

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

Figure 7-6 shows address connections of the e500 core and L2/SRAM.

Figure 7-6. Address Bus Connection of CCB

In SRAM mode, if a non–cache-line read or write transaction is not preceded by a cache-line write,

an ECC error occurs; such a non–cache-line write transaction cannot be allocated in the L2.

7.3

Memory Map/Register Definition

Table 7-1 shows the memory map for the L2/SRAM registers. Undefined 4-byte address spaces

within offset 0x000–0xFFF are reserved.

Table 7-1. L2/SRAM Memory-Mapped Registers

Offset

Access

Reset

Section/Page

0x2_0000

L2CTL—L2 control register

R/W

0x2000_0000

7.3.1.1/7-7

0x2_0010

L2CEWAR0—L2 cache external write address register 0

R/W

0x0000_0000

7.3.1.2/7-10

0x2_0018

L2CEWCR0—L2 cache external write control register 0

R/W

0x0000_0000

7.3.1.3/7-10

0x2_0020

L2CEWAR1—L2 cache external write address register 1

R/W

0x0000_0000

7.3.1.2/7-10

0x2_0028

L2CEWCR1—L2 cache external write control register 1

R/W

0x0000_0000

7.3.1.3/7-10

0x2_0030

L2CEWAR2—L2 cache external write address register 2

R/W

0x0000_0000

7.3.1.2/7-10

0x2_0038

L2CEWCR2—L2 cache external write control register 2

R/W

0x0000_0000

7.3.1.3/7-10

0x2_0040

L2CEWAR3—L2 cache external write address register 3

R/W

0x0000_0000

7.3.1.2/7-10

0x2_0048

L2CEWCR3—L2 cache external write control register 3

R/W

0x0000_0000

7.3.1.3/7-10

0x2_0100

L2SRBAR0—L2 memory-mapped SRAM base address

R/W

0x0000_0000

7.3.1.4/7-11

0x2_0108

L2SRBAR1—L2 memory-mapped SRAM base address

R/W

0x0000_0000

7.3.1.4/7-11

0x2_0E00

L2ERRINJHI—L2 error injection mask high register

R/W

0x0000_0000

7.3.1.5.1/7-13

0x2_0E04

L2ERRINJLO—L2 error injection mask low register

R/W

0x0000_0000

7.3.1.5.1/7-13

0x2_0E08

L2ERRINJCTL—L2 error injection tag/ECC control register

R/W

0x0000_0000

7.3.1.5.1/7-13

0x2_0E20

L2CAPTDATAHI—L2 error data high capture register

0x0000_0000

7.3.1.5.2/7-15

0x2_0E24

L2CAPTDATALO—L2 error data low capture register

0x0000_0000

7.3.1.5.2/7-15

MSTR

e500 Core

L2/SRAM

SNOOP

ADDR_IN

e500 Coherency Module

(ECM)

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