MPC8540 datasheet(307/1302 Pages) FREESCALE

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Cache Organization

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-3

— Flash clearing of all instruction and/or data locks is done by writes to configuration

registers

— An unlock attribute attached to a read instruction.

•

Error injection modes for testing

SRAM features include the following:

•

I/O devices access SRAM regions by marking transactions as snoopable (global)

•

Regions can reside at any aligned location in the memory map

•

For accesses of less than a cache-line, byte-accessible ECC is protected using

read-modify-write transactions.

7.2

Cache Organization

When the entire 256-Kbyte array is used as a cache, it has two banks each containing 512 sets of

eight cache blocks (eight ways), as shown in Figure 7-2. Each block consists of 32 bytes of data

and an address tag.

Figure 7-2. Cache Organization

512 Sets

Block 5

Block 6

Block 7

Way 4

Address Tag 4

Address Tag 5

Address Tag 6

Address Tag 7

Way 1

Way 2

Way 3

Way 0

Address Tag 0

Address Tag 1

Address Tag 2

Address Tag 3

Words [0–7]

8 Words/Block

512 Sets

Way 5

Way 6

Way 7

Way 4 Address Tag 4

Address Tag 5

Address Tag 6

Address Tag 7

Way 1

Way 2

Way 3

Way 0 Address Tag 0

Address Tag 1

Address Tag 2

Address Tag 3

Words [0–7]

Bank 1

Bank 0

8 Words/Block

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