MPC8540 datasheet(306/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

7-2

Freescale Semiconductor

L2 Look-Aside Cache/SRAM

7.1.1

L2 Cache and SRAM Features

Two 128-Kbyte arrays can be designated independently as externally-accessible memory-mapped

SRAM or cache. The L2 cache has the following characteristics:

•

Write-through, front-side cache

— Front-side design provides easier cache access for I/O masters such as Ethernet and RapidIO

— Write-through design is more efficient on the processor bus for front-side caches

•

Valid, locked, and stale states (no modified state)

•

Two input data buses (64 and 128 bits) and one output data bus (128 bits wide)

•

All accesses are fully pipelined and non-blocking (allows hits under misses)

•

256-Kbyte array organized as 1024 eight-way sets of 32-byte cache lines

•

Eight-way set associativity (high level of associativity yields good performance even with

many locked lines)

•

Tag arrays contain 17 tag bits and 1 tag parity bit per line to support 256-Kbyte cache

(1024 sets), or 18 tag bits to support 128-Kbyte cache (512 sets).

•

Configurable to allocate processor instructions, data, or both

— Allows external writes (stashing) to allocate and optionally lock a line using one of the

two following methods:

– Attributes attached to the transactions by initiator or ATMU

– I/O devices can force memory writes to be allocated using programmed memory ranges

•

Pseudo-LRU (7-bit replacement algorithm)

•

Data ECC on 64-bit boundaries (single-error correction, double-error detection)

•

Tag parity for 256-Kbyte mode (1 tag bit per line covering cache tags)

•

Cache locking methods

— Individual line locks are set and cleared by using e500 cache locking APU instructions—

Data Cache Block Touch and Lock Set (dcbtls), Data Cache Block Touch for Store and

Lock Set (dcbtstls), and Instruction Cache Block Touch and Lock Set (icbtls).

— A lock attribute can be attached to write operations.

— Individual line locks are set and cleared through core-initiated instructions, by external

reads or writes, or by accesses to programmed memory ranges defined in L2 cache

external write address registers (L2CEWARn).

— The entire cache can be locked by setting a configuration register appropriately.

•

Lock clearing methods

— Individual locks cleared by cache locking APU instructions (Instruction Cache Block

Lock Clear (icblc) and Data Cache Block Lock Clear (dcblc)) or by snooped flush

unless entire cache is locked

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