MPC8540 datasheet(302/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-52

Freescale Semiconductor

Core Register Summary

6.15.1 Global Control Register 0 (PMGC0, UPMGC0)

6.15.2 Local Control A Registers

(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)

Field FAC PMIE FCECE

—

Reset

All zeros

R/W

PMGC0: Supervisor R/W; UPMGC0: User read-only

PMR

PMGC0: PMR400; UPMGC0: PMR384

Figure 6-56. Performance Monitor Global Control Register 0 (PMGC0),

User Performance Monitor Global Control Register 0 (UPMGC0)

Table 6-40. PMGC0 Field Descriptions

Bits

Name

Description

FAC

Freeze all counters. When FAC is set by hardware or software, PMLCx[FC] maintains its current

value until it is changed by software.

0 The PMCs are incremented (if permitted by other PM control bits).

1 The PMCs are not incremented.

PMIE

Performance monitor interrupt enable

0 Performance monitor interrupts are disabled.

1 Performance monitor interrupts are enabled and occur when an enabled condition or event occurs.

FCECE Freeze counters on enabled condition or event

0 The PMCs can be incremented (if permitted by other PM control bits).

1 The PMCs can be incremented (if permitted by other PM control bits) only until an enabled

condition or event occurs. When an enabled condition or event occurs, PMGC0[FAC] is set. It is

up to software to clear FAC.

35–63

—

Reserved, should be cleared.

37 38

40 41

47 48

Field FC FCS FCU FCM1 FCM0 CE

—

EVENT

Reset

All zeros

R/W

PMLCa0–PMLCa3: Supervisor R/W

UPMLCa0–UPMLCa3: User read-only

PMR

PMLCa0: PMR144, PMLCa1: PMR145, PMLCa2: PMR146, PMLCa3: PMR147

UPMLCa0: PMR128, UPMLCa1: PMR129, UPMLCa2: PMR130, UPMLCa3: PMR131

Figure 6-57. Local Control A Registers (PMLCa0–PMLCa3),

User Local Control A Registers (UPMLCa0–UPMLCa3)

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