MPC8540 datasheet(299/1302 Pages) FREESCALE

299 / 1302 page

Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-49

FINVH

Embedded floating-point invalid operation error high. Set when an input value on the high side is a

NaN, Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero.

FDBZH Embedded floating-point divide by zero error high. Set if the dividend is non-zero and the divisor is

zero.

FUNFH Embedded floating-point underflow error high

FOVFH Embedded floating-point overflow error high

40–41

—

Reserved, should be cleared.

FINXS

Embedded floating-point inexact sticky. FINXS = FINXS | FGH | FXH | FG | FX

FINVS

Embedded floating-point invalid operation sticky. Location for software to use when implementing true

IEEE floating point.

FDBZS Embedded floating-point divide by zero sticky. FDBZS = FDBZS | FDBZH | FDBZ

FUNFS Embedded floating-point underflow sticky. Storage location for software to use when implementing

true IEEE floating point.

FOVFS Embedded floating-point overflow sticky. Storage location for software to use when implementing true

IEEE floating point.

MODE

Embedded floating-point mode (read only on e500)

SOV

Integer summary overflow. Set whenever an SPE instruction (except mtspr) sets OV. SOV remains

set until it is cleared by mtspr[SPEFSCR].

Integer overflow. An overflow occurred in the lower half of the register while a SPE integer instruction

is being executed.

Embedded floating-point guard bit. Floating-point guard bit from the lower half. The value is undefined

if the processor takes a floating-point exception due to input error, floating-point overflow, or

floating-point underflow.

Embedded floating-point sticky bit. Floating bit from the lower half. The value is undefined if the

processor takes a floating-point exception due to input error, floating-point overflow, or floating-point

underflow.

FINV

Embedded floating-point invalid operation error. Set when an input value on the high side is a NaN,

Inf, or Denorm. Also set on a divide if both the dividend and divisor are zero.

FDBZ

Embedded floating-point divide by zero error. Set of the dividend is non-zero and the divisor is zero.

FUNF

Embedded floating-point underflow error

FOVF

Embedded floating-point overflow error

—

Reserved, should be cleared.

FINXE

Embedded floating-point inexact enable

FINVE

Embedded floating-point invalid operation/input error exception enable

0 Exception disabled

1 Exception enabled

If the exception is enabled, a floating-point data exception is taken if FINV or FINVH is set by a

floating-point instruction.

Table 6-36. SPEFSCR Field Descriptions (continued)

Bits

Name

Function

MPC8540 Datasheet(PDF) 299 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 299 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL