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MPC8540 Datasheet(PDF) 303 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 303 Page - Freescale Semiconductor, Inc |
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303 / 1302 page  Performance Monitor Registers (PMRs) MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 6-53 6.15.3 Local Control B Registers (PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) Table 6-41. PMLCa0–PMLCa3 Field Descriptions Bits Name Description 32 FC Freeze counter 0 The PMC is incremented (if permitted by other PM control bits). 1 The PMC is not incremented. 33 FCS Freeze counter in supervisor state 0 The PMC is incremented (if permitted by other PM control bits). 1 The PMC is not incremented if MSR[PR] = 0. 34 FCU Freeze counter in user state 0 The PMC is incremented (if permitted by other PM control bits). 1 The PMC is not incremented if MSR[PR] = 1. 35 FCM1 Freeze counter while mark = 1 0 The PMC is incremented (if permitted by other PM control bits). 1 The PMC is not incremented if MSR[PMM] = 1. 36 FCM0 Freeze counter while mark = 0 0 The PMC is incremented (if permitted by other PM control bits). 1 The PMC is not incremented if MSR[PMM] = 0. 37 CE Condition enable 0PMCx overflow conditions cannot occur (PMCx cannot cause interrupts, cannot freeze counters) 1 Overflow conditions occur when the most-significant bit of PMCx is equal to 1. It is recommended that CE be cleared when counter PMCx is selected for chaining. 38–40 — Reserved, should be cleared. 41–47 EVENT Event selector. Up to 128 events selectable. These events are described in the PowerPC e500 Core Reference Manual. 48–63 — Reserved, should be cleared. 32 52 53 55 56 57 58 63 Field — THRESHMUL — THRESHOLD Reset All zeros R/W PMLCb0–PMLCb3: Supervisor R/W UPMLCb0–UPMLCb3: User read-only PMR PMLCb0: PMR272, PMLCb1: PMR273, PMLCb2: PMR274, PMLCb3: PMR275 UPMLCb0: PMR256, UPMLCb1: PMR257, UPMLCb2: PMR258, UPMLCb3: PMR259 Figure 6-58. Local Control B Registers (PMLCb0–PMLCb3), User Local Control B Registers (UPMLCb0–UPMLCb3) |
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